# Design a four input gate: [(a+b+c)d]’. (1) Show the transistor level schematic of your design. (2) Order the inputs so that

Question # 40012 | 4 years ago |
---|

$15 |
---|

Homework 3 (complete details are in attached file

1. Design a four input gate: [(a+b+c)d]’.

(1) Show the transistor level schematic of your design.

(2) Order the inputs so that the gate can be implemented using a single strip pdiff and

single strip ndiff.

(3) Show the stick diagram of the gate.

(4) Size the transistors so that each PDN and PUN has the same resistance as an

inverter with 2:1 PMOS and NMOS size;

(5) Estimate the minimum height and width of the gate from the stick diagram.

(6) Which input patterns give the longest tphl and tplh?

(7) Which input patterns give the shortest tphl and tplh?

2. Consider the following circuit.

a. What is the logic function implemented by the CMOS transistor network? Size

the NMOS and PMOS so that the output resistance is the same as that of an

inverter with an NMOS W/L=1 and PMOS W/L=2.

b. What are the input patterns that give the worst case tpHL and tpLH. State clearly

what are the initial input patterns and which inputs has to make a transition in

order to achieve this maximum propagation delay. Consider the effect of the

capacitances at the internal nodes.

c. If P(A=1)=0.5, P(B)=1=0.2, P(C=1)=0.3, and P(D=1)=1, determine the power

dissipation in the logic gate. Assume VDD=2.5V, Cout = 30fF and fclk = 250MHZ.

3. Compare two different implementations of a 6 input AND circuit: O=ABCDEF. First,

implement it as a 6 input NAND gate plus an inverter. Second, implement it using 3-

input NAND gates and 2-input NOR gates. For both implementations, perform the

following tasks:

(1) Draw the stick diagram and estimate the size. Assume that the height of the standard

cell is 12 tracks and all cells are place in the same row. (Tips: Try to share contacts as

much as possible.)

(2) Estimate the minimum width of your design.

(2) Identify the input patterns that give the best and worst propagation delay.

4.

4